1. Field of the Invention
Embodiments of the present invention relate generally to a semiconductor memory device. More particularly, embodiments of the invention relate to a semiconductor memory device capable of selectively refreshing word lines included therein.
A claim of priority is made to Korean Patent Application No. 10-2005-0008119, filed on Jan. 28, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
A conventional Dynamic Random Access Memory (DRAM) comprises a plurality of DRAM memory cells, each comprising a single transistor and a single capacitor. A DRAM memory cell stores data by charging the capacitor and it reads data by detecting the amount of charge on the capacitor, i.e., the capacitor's voltage. Where the amount of charge on the capacitor exceeds a predetermined threshold value, the DRAM cell stores a first logic state (e.g., logical ‘1’). On the other hand, where the amount of charge on the capacitor is below the threshold value, the DRAM cell stores a second logic state (e.g., logical ‘0’).
Unfortunately, the charge stored in the capacitor tends to decay over time. Accordingly, DRAM memory cells need to be periodically refreshed to maintain their stored data values. If a DRAM memory cell is not periodically refreshed, for example, if the DRAM's power supply is disconnected, the DRAM memory cell loses its stored data.
One problem with the conventional techniques for refreshing DRAM memory cells is that the conventional techniques refresh memory cells regardless of whether they store any charge. For instance, where all of the DRAM memory cells connected to a word line store the second logic state, conventional techniques still perform a refresh operation on those DRAM memory cells. Since the refresh operation takes time and consumes power, performing unnecessary refresh operations can impair a DRAM's performance.